The present disclosure relates to a wiring structure of a semiconductor integrated circuit device which includes multilayer wiring layers.
As a result of the progress in miniaturization, the techniques of positioning a dummy via have been used in the semiconductor fabrication process to increase uniformity of a multilayer wiring structure when forming a via hole. Specifically, physical restrictions on via density for assuring planarization are determined as design rules for layout design, and a dummy via is positioned to meet the physical restrictions on via density. The dummy via avoids isolation of an effective via and contributes to achieve a planar device surface.
Japanese Laid-Open Patent Application Publication No. 2007-305713 discloses an example technique of positioning a dummy via efficiently.